Image Decompressor - Hardware Implementation

Project Overview

Introduction:

  • Title: Image Decompressor - Hardware Implementation
  • Duration: October 2024 - December 2024
  • Role: Project Engineer
  • Technologies Used:SystemVerilog, UART communications, SRAM storage, Altera DE2-115 FPGA

Summary:
Developed a hardware-based image decompression system leveraging the Altera DE2-115 FPGA and implemented using SystemVerilog. This project demonstrates expertise in designing efficient digital systems for real-time image reconstruction, integrating modules for UART communication, SRAM storage, and VGA display, while ensuring optimized performance and resource utilization for high-speed data processing.

Objectives:

  1. Real-Time Decompression: Implement an efficient hardware-based image decompression system for real-time data processing and visualization.
  2. System Integration: Seamlessly integrate UART communication, SRAM storage, and VGA display modules for reliable image rendering.
  3. Algorithm Implementation: Design and optimize modules for lossless decoding, dequantization, and inverse discrete cosine transform (IDCT) using SystemVerilog.
  4. Performance Optimization: Ensure resource efficiency and meet strict timing constraints for consistent high-speed operation.

Technologies and Tools:

  • Hardware Platform: Altera DE2-115 FPGA Development Board
  • Programming Languages: SystemVerilog (hardware design and implementation)
  • Software & Tools: Quartus Prime (FPGA design), ModelSim (simulation)
  • Protocols: UART (data transmission), SRAM (memory interfacing), VGA (image display)

Project Achievements

  • Efficient Hardware Decompression: Successfully implemented a hardware-based image decompression system using SystemVerilog on the Altera DE2-115 FPGA.
  • Real-Time Image Reconstruction: Achieved real-time image processing and rendering through optimized UART communication, SRAM storage, and VGA display modules.
  • Optimized Resource Utilization: Ensured efficient use of FPGA resources while meeting strict timing constraints for reliable operation.

Gallery/Visuals

System Diagram

Challenges and Solutions

  • Challenge: Implementing efficient real-time image decompression on hardware with limited resources.
  • Solution: Optimized SystemVerilog code to balance resource utilization and performance, ensuring minimal hardware overhead while maintaining speed.
  • Challenge: Synchronizing data flow across UART, SRAM, and VGA interfaces.
  • Solution: Designed a state machine to manage data flow between communication, storage, and display modules, preventing bottlenecks and ensuring smooth operation.

Future Directions

  • Enhanced Compression Techniques: Integrate advanced compression algorithms to improve image quality and reduce processing time.
  • Scalability: Adapt the system for higher-resolution images and larger datasets while maintaining real-time performance.
  • Modular Design: Develop modular components to facilitate integration with other FPGA-based image processing systems.